The present invention generally relates to intermittent direct memory access (DMA) control systems, and more particularly to an intermittent DMA control system which intermittently carries out a DMA in data blocks and resumes the DMA after ending a software process required by a central control unit.
In certain kinds of data communication equipment, a hard disk or a floppy disk is provided with respect to a central control unit. In such data communication equipment, data transmission and reception are made between a main memory of the central control unit and a file memory control unit which controls write and read with respect to the hard disk or floppy disk. Data transmission and reception between the main memory and the file memory control unit are made intermittently in predetermined data blocks by DMA.
When carrying out such an intermittent DMA, it is desirable to improve the data transfer speed to and from the file memory regardless of the communication speed between the main memory and the file memory control unit.
FIG. 1 shows an example of a conventional intermittent DMA control system. The intermittent DMA control system shown in FIG. 1 includes a central control unit (CC) 11 which controls the entire system, a bus 12 of the central control unit 11, a main memory (MM) 13 which stores programs of the system and the like, a floppy disk unit (FD) 14, a hard disk unit (HD) 15, a file memory control unit (FMC) 16 which controls the floppy disk unit 14 and the hard disk unit 15, and an external bus control (PBC) unit 19 which carries out a bus control between the bus 12 of the central control unit 11 and the file memory control unit 16. The file memory control unit 16 includes an input side bus 17, an output side bus 18, a microprocessor unit (MPU) 20, dual port buffer memories (BM0) 21 and (BM1) 22, a DMA controller (DMAC1) 23 which controls DMA requests, a floppy disk controller (FDC) 24 which controls the floppy disk unit 14, and a small computer system interface (SCSI) protocol controller (SPC) 25 which controls the hard disk unit 15. The external bus control unit 19 includes a DMA controller (DMAC0) 26 which controls the DMA transfer.
The central control unit 11 is coupled to the main memory 13 and the external bus control unit 19 via the bus 12. The central control unit 11 transmits and receives instructions, data and the like between the main memory 13 and the floppy disk unit 14 or the hard disk unit 15 by controlling the file memory control unit 16 via the external bus control unit 19 using programs stored in the main memory 13. The buffer memories 21 and 22 of the file memory control unit 16 temporarily store the instructions, data and the like when transferring the same.
The transmission and reception of the instructions and data between the main memory 13 and the file memory control unit 16 are made by DMA transfer based on the control of the DMA controller 26 of the external bus control unit 19. This DMA transfer is successively made between the main memory and the buffer memories 21 and 22 of the file memory control unit 16. The transmission and reception of instructions, data and the like between the buffer memories 21 and 22 and the floppy disk control unit 24 or the SCSI protocol controller 25 are made by DMA transfer based on the control of the DMA controller 23. In addition, the DMA controller 23 generates a DMA request which requests DMA transfer with respect to the external bus control unit 19. The microprocessor unit 20 controls various parts of the file memory control unit 16.
FIG. 2 shows an operation time chart of the conventional intermittent DMA control system shown in FIG. 1. A description will now be given of the data transfer and the like in the conventional intermittent DMA control system with reference to FIG. 2, and the write transfer operation from the main memory 13 to the floppy disk controller 24 or the SCSI protocol controller 25 in particular.
First, a data transfer command is written from the central control unit 11 to the file memory control unit 16. The file memory control unit 16 which receives the data transfer command sets the DMA controller 23 so as to output a DMA request DMAREQ which requests DMA transfer with respect to the DMA controller 26 of the external bus control unit 19. Hence, the DMA request DMAREQ is output from the DMA controller 23. Responsive to this DMA request DMAREQ, the DMA controller 26 puts the central control unit 11 to a halt state, and starts a data transfer between the main memory 13 and the buffer memory 21. The halt state of the central control unit 11 continues during the time in which the DMA request DMAREQ is output.
The DMA controller 26 returns a DMA acknowledge DMAACK every time the DMA request DMAREQ is received from the DMA controller 23. At the same time, the DMA controller 26 reads a predetermined amount of data and the like from the main memory 13 and writes the read data and the like into the buffer memory 21. Such a process is repeated until the buffer memory 21 becomes full.
When the buffer memory 21 becomes full, the firmware of the microprocessor unit 20 of the file memory control unit 16 generates a communication start command. As a result, the floppy disk controller 24 or the SCSI protocol controller 25 outputs a data request DREQ if data write is possible. Responsive to the data request DREQ, the DMA controller 23 outputs an acknowledge ACK and transfers the data and the like within the buffer memory 21 to the floppy disk controller 24 or the SCSI protocol controller 25 by DMA transfer. Accordingly, data write is made with respect to the floppy disk unit 14 or the hard disk unit 15. The DMA controller 23 maintains the microprocessor unit 20 in the halt state during the DMA transfer.
During the data transfer from the buffer memory 21 to the floppy disk controller 24 or the SCSI protocol controller 25, the DMA controller 26 of the external bus control unit 19 makes a data transfer between the main memory 13 and the buffer memory 22. If the buffer memory 22 becomes full before the data transfer between the buffer memory 21 and the floppy disk controller 24 or the SCSI protocol controller 25 ends, the DMA controller 23 stops outputting the DMA request DMAREQ, and consequently, the external bus control unit 19 cancels the halt state of the central control unit 11 until the next DMA request DMAREQ is output.
Next, when the data transfer from the buffer memory 21 ends, the DMA controller 23 outputs the DMA request DMAREQ. Hence, the data transfer from the main memory 13 to the buffer memory 21 is resumed.
The above described operation is repeated until all of the data to be transferred is transferred from the main memory 13. Therefore, an intermittent DMA transfer is made between the main memory 13 and the floppy disk controller 24 or the SCSI protocol controller 25.
On the other hand, in the conventional intermittent DMA control system shown in FIG. 1, the read transfer operation from the floppy disk controller 24 or the SCSI protocol controller 25 to the main memory 13 is made as follows.
First, a data transfer command is transmitted from the central control unit 11 to the file memory control unit 16. Responsive to the data transfer command, the file memory control unit 16 puts the microprocessor unit 20 in the halt state, and starts a data transfer from the floppy disk controller 24 or the SCSI protocol controller 25 to the buffer memory 21 depending on the control of the DMA controller 23.
When the buffer memory 21 becomes full, a data transfer is made from the floppy disk controller 24 or the SCSI protocol controller 25 to the buffer memory 22, and at the same time, a DMA request DMAREQ is output from the file memory control unit 16. As a result, the DMA controller 26 puts the central control unit 11 to the halt state, and starts a data transfer from the buffer memory 21 to the main memory 13. If the data transfer from the buffer memory 21 to the main memory 13 ends before the data transfer from the floppy disk controller 24 or the SCSI protocol controller 25 to the buffer memory 22 ends, the output of the DMA request DMAREQ from the file memory control unit 16 stops and the DMA controller 26 cancels the halt state of the central control unit 11 until the next DMA request DMAREQ is output.
The above described operation is repeated until all of the data to be transferred is transferred from the floppy disk unit 14 or the hard disk unit 15. Hence, an intermittent DMA transfer is made between the floppy disk controller 24 or the SCSI protocol controller 25 and the main memory 13.
If the data transfer speed from the main memory 13 to the buffer memories 21 and 22 is sufficiently large compared to the data transfer speed from the buffer memories 21 and 22 to the floppy disk controller 24 or the SCSI protocol controller 25, the halt state of the central control unit 11 is cancelled at appropriate time intervals for appropriate times. However, if the difference between the two data transfer speeds is very small or zero or, the data transfer speed from the main memory 13 to the buffer memories 21 and 22 is slower, the time intervals at which the halt state of the central control unit 11 is cancelled may become long or the time in which the halt state is cancelled may become short.
On the other hand, the central control unit 11 makes a software operation which needs to be carried out periodically during the time in which the halt state is cancelled, such as monitoring the timer. However, if the data transfer speed from the main memory 13 to the buffer memories 21 and 22 is slower than the data transfer speed from the buffer memories 21 and 22 to the floppy disk controller 24 or the SCSI protocol controller 25, the halt state is not cancelled for a sufficiently long time, and there is a problem in that the central control unit 11 cannot carry out the software operation which needs to be carried out periodically.